Processor systems may utilise a common memory store (for example flash memory) for instructions and data. There may therefore be a need to control access to that memory to avoid conflicts between instruction read and data read and write processes.
In single-processor systems managing interactions is relatively straightforward as processor interrupts can be paused while data is written or erased. However, this is significantly more complex for dual-processor systems in which both processors are fetching their instructions from the same memory.
Global Navigation Satellite System (GNSS) is a standard generic term for navigation systems utilising signals from satellites to calculate position. Maintaining a lock on the satellite signals is very challenging, particularly in harsh urban environments. Blocking processor access to allow data storage exacerbates such challenges and losing lock, large position errors, or loss of synchronisation can easily occur without careful system design.
There is therefore a need for a means to manage memory access of dual-processor systems, particularly for GNSS devices, and a means to recover processor operation after memory access.